#ifndef _TILE64_REGISTERS_H_
#define _TILE64_REGISTERS_H_

enum tile64_register
{
	TILE64_REG_R0 = 0,
	TILE64_REG_R1 = 1,
	TILE64_REG_R2 = 2,
	TILE64_REG_R3 = 3,
	TILE64_REG_R4 = 4,
	TILE64_REG_R5 = 5,
	TILE64_REG_R6 = 6,
	TILE64_REG_R7 = 7,
	TILE64_REG_R8 = 8,
	TILE64_REG_R9 = 9,
	TILE64_REG_R10 = 10,
	TILE64_REG_R11 = 11,
	TILE64_REG_R12 = 12,
	TILE64_REG_R13 = 13,
	TILE64_REG_R14 = 14,
	TILE64_REG_R15 = 15,
	TILE64_REG_R16 = 16,
	TILE64_REG_R17 = 17,
	TILE64_REG_R18 = 18,
	TILE64_REG_R19 = 19,
	TILE64_REG_R20 = 20,
	TILE64_REG_R21 = 21,
	TILE64_REG_R22 = 22,
	TILE64_REG_R23 = 23,
	TILE64_REG_R24 = 24,
	TILE64_REG_R25 = 25,
	TILE64_REG_R26 = 26,
	TILE64_REG_R27 = 27,
	TILE64_REG_R28 = 28,
	TILE64_REG_R29 = 29,
	TILE64_REG_R30 = 30,
	TILE64_REG_R31 = 31,
	TILE64_REG_R32 = 32,
	TILE64_REG_R33 = 33,
	TILE64_REG_R34 = 34,
	TILE64_REG_R35 = 35,
	TILE64_REG_R36 = 36,
	TILE64_REG_R37 = 37,
	TILE64_REG_R38 = 38,
	TILE64_REG_R39 = 39,
	TILE64_REG_R40 = 40,
	TILE64_REG_R41 = 41,
	TILE64_REG_R42 = 42,
	TILE64_REG_R43 = 43,
	TILE64_REG_R44 = 44,
	TILE64_REG_R45 = 45,
	TILE64_REG_R46 = 46,
	TILE64_REG_R47 = 47,
	TILE64_REG_R48 = 48,
	TILE64_REG_R49 = 49,
	TILE64_REG_R50 = 50,
	TILE64_REG_R51 = 51,
	TILE64_REG_R52 = 52,
	TILE64_REG_TP = 53,
	TILE64_REG_SP = 54,
	TILE64_REG_LR = 55,
	TILE64_REG_SN = 56,
	TILE64_REG_IDN0 = 57,
	TILE64_REG_IDN1 = 58,
	TILE64_REG_UDN0 = 59,
	TILE64_REG_UDN1 = 60,
	TILE64_REG_UDN2 = 61,
	TILE64_REG_UDN3 = 62,
	TILE64_REG_ZERO = 63
};

#endif // !defined(_TILE64_REGISTERS_H_)
